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Jose Antonio Luque wrote:
Hi,
the cpu detection is wrong.
No, it's perfectly correct.
Only Pentiums X have SSE with this detection rutine, but this is wrong.
I don't have an AthlonXP/MP, but if you can write the SSE detection routine
for those CPUs, then I'd be greatful.
Some AMD and others machines have a MMX+ extension that is equivalent to
SSE.
Hum, no, they are are not equivalent. SSE contains MMX+, but MMX+ doesn't
contain all the SSE instructions.
My Duron supports MMX+ and if I enable SSE (out of Allegro) they
use the SSE routines. Example: masked_blit16 SSE scores 9600 and
masked_blit16 MMX scores 8600, this is a great improvement and others
procesors can use this feature.
You see, this is another problem. The Athlon Thunderbird and regular athlons
get *lower* scores on masked_blit when MMX+ is used. So what should I do
now? Durons have the same CPU ID, stepping and model as the TBird, but less
L2 cache, and run at a lower bus frequency. So how do I differentiate the
two? What about those new Durons who run like the old TBirds using the
Morgan core?
we have to rewrite the cpu detection and why not add some extra
information of CPUs as name, L1/L2 size, speed and others.
I agree to this. I'll submit a patch sometime next week. There'll be a
single variable called cpu_capabilities (like gfx_capabilities), where you
can check for flags.
Bit0: MMX
Bit1: MMX+
Bit2: SSE
Bit3: SSE2
Bit4: 3dNow!
Bit5: 3dNow!+
Bit6: cmov supported
and so on.
Another thing
cpu_3dnow=2 is 3DNow!+ or Extended 3DNow! not 3DNow! (test.c bug)
What about the additions to the AthlonXP? Super Extended 3dNow!?
cpu_sse=1 is SSE/MMX+ (with new detection rutine if you like)
Like I said, this is not the case.
--
- Robert J Ohannessian
"Microsoft code is probably O(n^20)" (my CS prof)
http://pages.infinit.net/voidstar/