[chrony-dev] [RFC] Support for raw memory mapped clock sources

[Enguerrand de Ribaucourt <enguerrand.de-ribaucourt@xxxxxxxxxxxxxxxxxxxx>]

Hello,

I have two embedded products which will have a GPS clock source 
connected to a Xilinx FPGA MPSoC. However, the GPS PPS and NMEA traffic 
will be routed to the programmable logic, not the Linux side.

The FPGA will be able to communicate the timestamps through some 
reserved memory connected with the Linux CPU cores. My idea is to reuse 
the existing SHM support of chrony. It does pretty much what I want: 
read a timestamp binary structure from a memory mapping.

However, the current SHM refclok implementation is specific to SHM 
devices, wherehas my FPGA's registers will appear within raw memory 
devices like /dev/mem, or /dev/uio.

I see two options for passing the raw memory structure to chrony:

 1. Write an additional middleware that maps the raw memory device and 
copies it regularly into an SHM device
 2. Add support for raw memory mappings to chrony, with lots of 
resemblance to the current refclock_shm.c implementation

Which approach would you recommend? If adding support to chrony makes 
sense for the general public, my company would likely be willing to 
contribute this upstream. We have multiple devices in different activity 
sectors with this hardware configuration. The options would look like:

 1. GPS -> FPGA -> AXI -> CPU -> /dev/uio -> middleware (custom) -> 
/dev/shm -> chrony
 2. GPS -> FPGA -> AXI -> CPU -> /dev/uio -> chrony (patched)

Also, I don't think using DMA should be necessary given the small size 
of the struct shmTime. For the PPS signal, the FPGA can connect share a 
GPIO, so I will use the pps-gpio driver.

Thank you for your time,

Enguerrand de Ribaucourt,
Savoir-faire Linux (FR)

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