[chrony-dev] Loop stability with PHC refclock

[Miroslav Lichvar <mlichvar@xxxxxxxxxx>]

With the new PHC refclock in git it's possible to collect samples at
very high rates (negative dpoll). I thought this would be a good
opportunity to make an experiment to see how stable is the loop with
very short polling intervals. With an Intel i210 card, I have used

refclock PHC /dev/ptp0 poll {0,1,2,3,4} dpoll -6 filter 4

That's 64 samples per second and only the last 4 in the polling
interval are used to control the system clock. I have processed the
raw data from refclocks.log with a median filter to reduce the noise,
and calculated offset RMS values and made some graphs.

poll0: 10.8 ns
poll1: 12.5 ns
poll2: 17.5 ns
poll3: 24.8 ns
poll4: 101.1 ns

http://mlichvar.fedorapeople.org/tmp/chrony_phc_poll0.png
http://mlichvar.fedorapeople.org/tmp/chrony_phc_poll1.png
http://mlichvar.fedorapeople.org/tmp/chrony_phc_poll2.png
http://mlichvar.fedorapeople.org/tmp/chrony_phc_poll3.png
http://mlichvar.fedorapeople.org/tmp/chrony_phc_poll4.png

It seems the loop is stable even at poll 0, at least with the PHC
refclock. This may not be the case with other refclocks (the PHC
refclock has the advantage over the PPS and SHM refclocks that there
is a very short delay between capturing the sample and the actual
processing in chrony).

-- 
Miroslav Lichvar

-- 
To unsubscribe email chrony-dev-request@xxxxxxxxxxxxxxxxxxxx with "unsubscribe" in the subject.
For help email chrony-dev-request@xxxxxxxxxxxxxxxxxxxx with "help" in the subject.
Trouble?  Email listmaster@xxxxxxxxxxxxxxxxxxxx.